A number of circuits have been devised to provide complementary (i.e. inverted and non-inverted) output pulses in response to a single clock input signal. Such circuits have a wide range of uses in digital logic systems. In particular, it is desirable to provide complementary pulses which occur essentially simultaneously with respect to each other. It is also desirable to provide substantially simultaneous complementary output pulses having a pulse width which is independent of the clock input signal pulse width, and which are generated with a minimum of delay following the leading edge of the clock input signal.
U.S. Pat. No. 4,617,477, entitled "Symmetrical Output Complementary Buffer", issued Oct. 14, 1986, to M. V. DePaolis, Jr. shows a CMOS (complimentary metal-oxide-semiconductor) circuit which, under certain design conditions, generates nearly symmetrical complimentary output signals, but the duration of those signals is dependent upon the duration of the input signal.
U.S. Pat. No. 4,645,947, entitled "Clock Driver Circuit", issued Feb. 24, 1987, to J. Prak shows a CMOS circuit which generates complementary pulses which are delayed with respect to the leading edge of the clock input signal.